Semiconductor devices such as an integrated circuit for driving a liquid crystal display panel (driver IC) and an integrated circuit for controlling auto-focusing of a digital still camera or the like (auto-focus IC) often include plural kinds of transistor devices (typically MOS FET transistors) having different breakdown voltages on a semiconductor substrate. Such a semiconductor device has, for example, a lower breakdown voltage region formed with a lower breakdown voltage transistor and a higher breakdown voltage region formed with a higher breakdown voltage transistor on the semiconductor substrate.
Isolation of device regions to be formed with the respective transistor devices is achieved by a LOCOS (local oxidation of silicon) method or an STI (shallow trench isolation) method. In the LOCOS method, a thermal oxide film is selectively grown on a surface of a silicon substrate for the isolation of the device regions. In the STI method, on the other hand, an insulating material (e.g., silicon oxide) is filled in a shallow trench (having a depth of about 4000 Å) formed in a silicon substrate for the isolation of the device formation regions.
For the semiconductor device including both the lower breakdown voltage region and the higher breakdown voltage region provided on the semiconductor substrate, it is a conventional practice to equally apply the LOCOS method to the respective regions (e.g., Japanese Unexamined Patent Publication Nos. HEI10-284615 (1998) and 2002-76288) or equally apply the STI method to the respective regions.
However, the application of the LOCOS method to the lower breakdown voltage region hinders microminiaturization of the device in the lower breakdown voltage region. On the other hand, the application of the STI method to the higher breakdown voltage region reduces the breakdown voltage due to remarkable concentration of the electric field on an edge of the trench.
More specifically, the MOS transistor of a higher breakdown voltage has a drift drain structure in which an oxide film thicker than a gate oxide film thereof is provided at an edge of a gate electrode thereof for alleviating the concentration of the electric field on the edge of the gate electrode. The thicker oxide film is formed as a LOCOS oxide film if the device isolation structure is provided by the LOCOS method, or formed as an STI portion if the device isolation structure is provided by the STI method. Where the thicker oxide film is formed as the STI portion, the electric field is liable to concentrate on an edge of the STI portion (an edge of the trench) located immediately below the edge of the gate electrode.
In the LOCOS method, on the other hand, a nitride film is formed on the surface of the silicon substrate with the intervention of a pad oxide film, and a resist film pattern is formed on the nitride film. The nitride film is etched by a reactive ion etching process using the resist film as a mask, whereby an opening is formed in the nitride film in association with a LOCOS oxide film formation region. After the resist film is removed, a thermal oxidation process is performed by using the nitride film as an oxidation resistant mask, whereby the thicker LOCOS oxide film grows in the opening of the nitride film. Thereafter, the nitride film is wet-etched by a hot phosphoric acid solution, and the pad oxide film is removed. Then, a thin gate oxide film is formed in a region isolated by the LOCOS oxide film.
However, the gate oxide film of the transistor provided in the lower breakdown voltage region and the gate oxide film of the transistor provided in the higher breakdown voltage region have completely different thicknesses. Therefore, the gate oxide film of the higher breakdown voltage transistor and the gate oxide film of the lower breakdown voltage transistor should be formed in separate steps.
That is, the thermal oxidation process should be performed selectively on the higher breakdown voltage region with the lower breakdown voltage region covered with the oxidation resistant mask when the gate oxide film of the higher breakdown voltage transistor is formed.
However, the hot phosphoric acid solution to be used for the removal of the nitride film serving as the oxidation resistant mask in the LOCOS method also dissolves the resist film. Therefore, the nitride film on the semiconductor substrate is completely removed by the wet etching process using the hot phosphoric acid solution, and the oxidation resistant mask in the lower breakdown voltage region is lost.
An alternative conceivable approach to the etching of the nitride film is to employ reactive ion etching. That is, a portion of the nitride film on the channel region is selectively dry-etched with the lower breakdown voltage region covered with the resist film.
Where the removal of the nitride film portion on the channel region is achieved by the reactive ion etching, however, the channel region is inevitably damaged by plasma. Therefore, if the gate oxide film is formed on the channel region thus damaged, it is impossible to provide a highly reliable gate oxide film, so that the transistor fails to have desired characteristics.
Where the STI (shallow trench isolation) method is employed for the isolation of the device regions, the aforementioned problems occur because the formation of the gate oxide film is achieved by the thermal oxidation method.
A specific example employing the LOCOS method is shown in FIGS. 10(a) to 10(d). As shown in FIG. 10(a), a thick LOCOS oxide film 3 is formed to isolate a lower breakdown voltage device region 4 and a higher breakdown voltage device region 5 by a selective thermal oxidation process using a nitride film pattern 2 formed on a semiconductor substrate 1 as a mask. Then, the nitride film 2 is removed and the thermal oxidation process is further performed, whereby a gate oxide film 6 is formed in the higher breakdown voltage device region 5 as shown in FIG. 10(b). At this time, an oxide film 6a grows in the lower breakdown voltage device region 4 in the same manner. As shown in FIG. 10(c), a resist film 7 is formed as having a pattern which covers the higher breakdown voltage device region 5 and uncovers the lower breakdown voltage device region 4, and the oxide film 6a (a hatched portion) in the lower breakdown voltage region 4 is removed by a fluoric acid solution with the use of the resist film 7 as a mask. In turn, as shown in FIG. 10(d), a gate oxide film 8 for the lower breakdown voltage device region 4 is formed by performing a thermal oxidation process after removing the resist film 7.
Thus, the three types of oxide films having different thicknesses, i.e., the LOCOS oxide film 3, the gate oxide film 6 thinner than the LOCOS oxide film 3, and the gate oxide film 8 thinner than the gate oxide film 6, are formed.
It would be ideal that the resist film 7 could be aligned with an edge of the lower breakdown voltage device region 4 isolated by the LOCOS oxide film 3, but the edge of the lower breakdown voltage device region 4 is present on the LOCOS oxide film 3 because a mask alignment margin should be taken into consideration. Therefore, the LOCOS oxide film is eroded during the wet etching as shown in FIG. 10(c), whereby a step 9 is formed.
This reduces the thickness of a part of the LOCOS oxide film 3, thereby causing deterioration of a device isolation breakdown voltage. This problem may be avoided by increasing the thickness of the LOCOS oxide film 3. However, this increases a bird's beak of the LOCOS oxide film 3, thereby sacrificing device size controllability.
Further, the step 9 is liable to reduce a focus margin for lithography to be performed in a later step, causing a problem associated with micro-processing.
FIGS. 11 and 12 are a schematic sectional view and a schematic plan view, respectively, for explaining the construction of a semiconductor device having a transistor of a drift drain structure. A pair of drift layers 103 are provided on opposite sides of a channel region 102 in a semiconductor substrate 101. A shallow trench 104 is partly located in surface portions of the drift layers 103 adjacent to the channel region 102. The trench 104 is filled with silicon oxide 105. A gate oxide film 106 is provided on a surface of the channel region 102. A gate electrode 107 (indicated by a two-dot-and-dash line in FIG. 12) is provided on the gate oxide film 106, and an edge portion of the gate electrode 107 reaches an upper surface of the silicon oxide 105. With this arrangement, the concentration of an electric field on the edge of the gate electrode 107 can be alleviated.
As shown in FIG. 12, the trench 104 is also located on opposite sides of the channel region 104 with respect to a widthwise direction W to provide an isolation structure for isolation of the transistor from other devices provided on the semiconductor substrate 101 (so-called shallow trench isolation).
FIGS. 13(a) to 13(f) are schematic sectional views illustrating the trench 104 on an enlarged scale for explaining a production process for the semiconductor device. As shown in FIG. 13(a), the trench 104 is formed by etching the semiconductor substrate 101 by reactive ion etching (RIE) using a silicon nitride film 111 as a hard mask. Thereafter, as shown in FIG. 13(b), a silicon oxide film 112 is formed on the entire surface of the resulting semiconductor substrate by a CVD (chemical vapor deposition) method. Then, as shown in FIG. 13(c), a planarization process is performed by a CMP (chemical mechanical polishing) method to expose the silicon nitride film 111, whereby silicon oxide 105 is buried in the trench 104.
In turn, as shown in FIG. 13(d), the silicon nitride film 111 is removed. Then, a diffusion process for formation of the drift regions 103 and other processes are performed. After each of the processes, the semiconductor substrate 101 is subjected to a cleaning process (light etching process) with the use of fluoric acid. Therefore, the thickness of the silicon oxide film 112 is reduced. The thickness reduction progresses isotropically, and the semiconductor substrate 101 is not soluble at all in fluoric acid. Therefore, the edge of the silicon oxide 105 is recessed inward of the edge of the trench 104 as shown in FIG. 13(e) before formation of the gate oxide film 106, so that a recess (divot) 113 (indicated by a bold line in FIG. 12) is formed on a boundary of the channel region 102.
In this state, the gate oxide film 106 is formed as shown in FIG. 13(f), and the gate electrode 107 is formed as extending from the channel region 102 to the upper side of the trench 104.
Therefore, the gate oxide film 106 has a thinner film portion 106a having a smaller thickness than other portions thereof on a boundary of the trench 104, i.e., on the edge of the channel region 104. The thinner film portion 106a causes reduction of the breakdown voltage of the gate oxide film and deterioration of static characteristics of the transistor (e.g., a hump which causes an unstable threshold).
FIGS. 14(a) to 14(d) schematically illustrate a production method for producing the semiconductor device having the transistor of the drift drain structure by employing the LOCOS method. As shown in FIG. 14(a), a nitride film 202 is formed on a semiconductor substrate 201, and patterned by using a resist film 210 as a mask. The nitride film 202 has a pair of openings 202a formed on opposite sides of a channel region 203. As shown in FIG. 14(b), LOCOS oxide films 204 are formed in a surface of the semiconductor substrate 201 by thermal oxidation with the use of the nitride film 202 as an oxidation resistant mask.
In turn, as shown in FIG. 14(c), a P-type well 205 is formed in the substrate by implanting ions and thermally diffusing (driving) the implanted ions after removing the nitride film 202. Further, a resist film 206 is formed as covering the channel region 203 and a portion of the substrate not formed with the well 205, and N-type impurity ions are implanted into the substrate by using the resist film 206 as a mask.
Thereafter, as shown in FIG. 14(d), the resist film 206 is peeled off, and the implanted N-type impurity ions are thermally diffused, whereby a pair of drift layers 207 are formed on the opposite sides of the channel region 203. The drift layers 207 extend to the channel region 203 below the LOCOS oxide films 204 on the opposite sides of the channel region 203. A thin gate oxide film 208 is formed in a surface portion of the semiconductor substrate 201 on the channel region 203 by a thermal oxidation method. The gate oxide film 208 is connected to the LOCOS oxide films 204. In this state, a gate electrode 209 is formed as covering an upper surface of the gate oxide film 208 and extending to upper surfaces of the LOCOS oxide films 204. Thus, an edge of the gate electrode 209 is located on the LOCOS oxide films 204 which are thicker than the gate oxide film 208, so that the concentration of an electric field on the edge of the gate electrode 209 can be alleviated.
However, the aforementioned production method suffers from a problem that an intrusion distance X by which the drift layers 207 each intrude into the channel region 203 from an inner edge of the LOCOS oxide film 204 varies. The variation in the intrusion distance X is attributable to misalignment (mask misalignment) between the resist film 210 as the mask for the patterning of the nitride film 202 and the resist film 206 as the mask for the formation of the drift layers 207. Therefore, the intrusion distance X varies depending on a wafer (semiconductor substrate 201) and also varies depending on an in-plane position on the same wafer.
As shown in FIG. 15, the intrusion distance X significantly influences the breakdown voltage of the transistor (BVdss: breakdown voltage of drain with source short). As can be understood from FIG. 15, the breakdown voltage is stabilized by increasing the intrusion distance X. However, a design having a greater intrusion distance X fails to satisfy the demand for the microminiaturization of the transistor, and merely provides a lower breakdown voltage. Therefore, it is desirable to reduce the intrusion distance X as much as possible and to minimize the variations.